YSC-7061U / YSC-7061D Up/Down Converter

PXIe Frequency Conversion for RF Signal Chain Integration

YSC-7061U and YSC-7061D form a compact PXIe-based frequency conversion solution for RF development, subsystem integration, and automated test platforms. The up-converter provides RF output from 400 MHz to 6 GHz, while the down-converter supports RF input from 20 MHz to 6 GHz.

Both modules use a 3U two-slot PXIe architecture and support parameter configuration, functional control, status monitoring, and reference clock configuration through the PXIe control interface with C/C++ host integration and Windows 10 compatibility.

Up-Converter (YSC-7061U)

Parameter	Value
IF Input Frequency	30 MHz to 110 MHz
IF Bandwidth	80 MHz
RF Output Frequency	400 MHz to 6 GHz
Output Power	-70 dBm to +13 dBm
Gain Flatness	≤ ±0.75 dB
Output P1dB	≥ 15 dBm
Link Gain	-70 dB to +20 dB
Spurs	< -60 dBc
Programmable Attenuation	0 dB to 90 dB, 1 dB step

Down-Converter (YSC-7061D)

Parameter	Value
RF Input Frequency	20 MHz to 6 GHz
Max Input Power	27 dBm
IF Output Frequency	70 MHz
IF Bandwidth	80 MHz
Max IF Output Power	15 dBm
Gain Range	25 ±3 dB (normal) / 40 ±3 dB (low-noise)
Output P1dB	≥ 15 dBm
RF Flatness	≤ ±0.75 dB
Input VSWR	< 2.5
Spurious Suppression	≤ 50 dB typ
Programmable Attenuation	0 dB to 60 dB, 1 dB step

Common Specifications

Parameter	Value
LO Phase Noise	< -100 dBc/Hz @ 10 kHz
Power Consumption	≤ 25 W per module
PXIe Form Factor	3U, 2 slots
Host Integration	C/C++ control library, Windows 10

Typical Applications

• PXIe-based RF subsystem integration — compact 3U two-slot form factor
• IF to RF up-conversion and RF to IF down-conversion — matched converter pair
• Automated RF validation and system debugging — C/C++ host control library
• Reference-clock synchronized test platforms — low phase noise LO architecture
• Custom signal chain development — programmable attenuation 0-90 dB